Seminar by Dr. Yin Chongxian

The development of SINAP timing system and upgrading: by Dr. Yin Chongxian (Electronic Group, SSRF/SINAP, Shanghai)
on January 7, 2011, 15:00-16:00, at KEKB Meeting room.; Presentation: [Pdf], [PowerPoint]; Abstract:
Thanks to the rapid development of high speed serial communication technology, the event timing system is the more and more sophisticated solution for timing system in accelerator facilities. Based on the event timing system structure, SINAP timing system provide a complete lists of hardware which could satisfied different requirement in accelerator’s timing system. The hardware of SINAP timing system includes EVG, EVR, EVR TTL VME transition board, EVR Optic VME transition board, FANOUT, Multimode fiber O/E, Optic fiber O/E. The 2.5Gbps fiber star network is implemented in SINAP timing system, on which EVG could broadcast all triggers and clocks in this fiber network. In the upgraded SINAP timing system, the data transfer function and fiber length compensation function will be added by the dedicated data frame format. The EVRs could exchange data with the fixed latency in the upgraded SINAP timing system. The potential implementations are the global orbit feedback system, the distributed fast interlock system and so on.

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