diff -urN src.org/MRF_CONFIG_SITE_vxWorks-ppc604_long src/MRF_CONFIG_SITE_vxWorks-ppc604_long --- src.org/MRF_CONFIG_SITE_vxWorks-ppc604_long 1970-01-01 09:00:00.000000000 +0900 +++ src/MRF_CONFIG_SITE_vxWorks-ppc604_long 2008-09-10 10:23:34.000000000 +0900 @@ -0,0 +1,545 @@ +#============================================================================== +# MRF_CONFIG_SITE +# +# Site-specific configuration parameters for building the MRF event system +# software libraries. +# +# This file is where you can specify site-specific information such as +# the speed of the event clock, or how the IOC processor handles geographic +# addressing. +# +# If you are building for more than one IOC target architecture, and each +# architecture has different site-specific configuration parameters, you can +# copy this file into separate architecture-specific files of the form: +# MRF_CONFIG_SITE_ +# where is the target architecture name. +# +# Any parameter values set in the MRF_CONFIG_SITE_ file will override +# the corresponding parameter vaules in the MRF_CONFIG_SITE file. This is +# particularly useful if your different target architectures have different +# ways of handling geographic addressing. +# +#------------------------------------------------------------------------------ +# Author: E.Bjorklund +# Date: 23 May 2006 +# +#------------------------------------------------------------------------------ +# Modification Log +# 23-May-2006 E.Bjorklund Original Version +# +#============================================================================== + + +############################################################################### +# PART I -- VME-64x Geographic Addressing Support +#============================================================================== +# The MRF timing boards use VME-64x "Geographic Addressing" to set the +# board's VME address through software instead of on-board jumpers. +# Geographic Addressing is supported through the "CR/CSR" address modifier +# (0x2f). In CR/CSR space, each VME slot is allocated 512K bytes divided into +# two sections: A "Configuration ROM" (CR) section , which contains static +# information such as the board and manufacturer ID codes, and a "Control and +# Status Register (CSR) section, which contains the registers for setting +# the board's VME address and address modifier. +# +# This section of the MRF_CONFIG_SITE file determines how the software +# accesses the CR/CSR space so that it can set the board's VME address. +# + +#------------------------------------------------------------------------------ +# Question 1: Does your version of EPICS support CR/CSR Addressing? +# +# Older versions of EPICS (prior to release R3.14.8.2) generally do not +# support CR/CSR addressing unless you have patched devLib. +# +# If you have an EPICS version that does not support CR/CSR addressing, then +# set EPICS_SUPPORTS_CRCSR = NO +# + +EPICS_SUPPORTS_CRCSR = YES +#EPICS_SUPPORTS_CRCSR = NO + +#------------------------------------------------------------------------------ +# Question 2: Does your Board Support Package support CR/CSR Addressing +# +# Most out-of-the-box vxWorks BSPs do not come with CR/CSR addressing support. +# There are, however, vxWorks and RTEM BSPs in the EPICS community that do. +# If your BSP does not support CR/CSR addressing, it is not terribly hard to +# modify it so that it does, although it would be helpful to at least find an +# example to follow. +# +# If your BSP does not support CR/CSR addressing, then it doesn't matter +# whether your EPICS version supports CR/CSR addressing or not. +# +# If know that your BSP supports CR/CSR addressing then set +# BSP_SUPPORTS_CRCSR = YES and skip down to Part II of this configuration +# file. Otherwise, set BSP_SUPPORTS_CRCSR = NO and answer the rest of the +# questions in this section. +# + +#BSP_SUPPORTS_CRCSR = YES +BSP_SUPPORTS_CRCSR = NO + +#------------------------------------------------------------------------------ +# Question 3: What is the path to your board support package's source code? +# +# Include the full path to the board support package used for your target +# architecture. For vxWorks systems, the path name typically ends with: +# .../target/config/ +# as shown in the example below. +# +# NOTE: Do not end the path string with a "/" character. +# + +#BSP_SOURCE_PATH = /ade/vxWorks/6.2/vxworks-6.2/target/config/mv5100 +BSP_SOURCE_PATH = /space/wind221/target/config/mv5500 +#------------------------------------------------------------------------------ +# Question 4: Does your BSP use "Supervisor" or "User" mode access in +# the A24 VME window? (defaults to "SUPERVISOR" if neither +# option is selected). +# +# The Event Generator and the VME Event Receiver cards are addressed in A24 +# space. Although geographic addressing allows you to place the card in any +# address space, the software enforces A24 space when it initializes the cards. +# +# Most board support packages define only one A24 window in the VME Bridge +# and set it use either the "A24 Supervisor Data" address modifier (0x3D) +# or the "A24 User Data" address modifier (0x39). Usually, one does not +# need to worry about which address modifier was selected by your BSP because +# most cards that use A24 addressing will support both modifiers. Currently, +# however, the MRF cards can only support one address modifier, so it is +# important to use the same modifier as the one set by the BSP. +# +# Since A24 space is mandated by the software, the only decision you need to +# make in this section is whether the A24 modifier should specify "Supervisor" +# or "User" mode access. The default value is to use "Supervisor" mode access +# because that seems to be the choice for most BSPs. Some of the newer vxWorks +# BSPs, however, are starting to map VME windows using the "User" mode address +# modifiers in order to support their user-mode "Real-Time-Package" (RTP) +# architecture. +# +# If you don't know which address modifier your BSP uses for the A24 window, +# then just select one of the answers below (you have a 50% chance of being +# right). Load the software onto an IOC that contains an Event Generator or +# an Event Recevier card and call either the "EgConfigure" or "ErConfigure" +# routine. If the routine fails with a message of the form: +# "Unable to read Event Generator/Receiver Card x (Slot y) at VME/A24 +# address ......", +# then you chose the wrong option. +# + +#ADDRESS_MODE = SUPERVISOR +#ADDRESS_MODE = USER + + +############################################################################### +# PART II -- PMC EVR Addressing +#============================================================================== +# This section pertains to the PMC version of the Event Receiver Card. +# If you are only using VME EVR cards, you can ignore this section and skip +# to Part III. +# + +#------------------------------------------------------------------------------ +# Question 1: Do the PMC EVRs use the MRF vendor and device codes for the +# subsystem ID? +# +# The PMC Event Receivers use a PLX Technology, Inc. PCI-9030 bridge chip +# to interface between the PCI bus and the EVR local bus. As a result, when +# the configuration software is looking for a PMC EVR card, it will use the +# PLX vendor and device ID codes to locate the device. The problem is that +# the PLX-9030 is a fairly generic device that could also be used to +# attach somebody else's device to the PCI bus. If this happens, the other +# device could be mistaken for a PMC EVR by the configuration software. +# +# To get around this problem, later versions of the PMC EVR ship with the +# MRF vendor and device IDs coded into the *SubSystem* vendor and device +# id fields to distinguish the PMC EVR from any other device that may be +# using the PLX-9030 bridge. +# +# The purpose of this question is to let the configuration software know if +# it should be looking for the MRF vendor and device codes or the PLX vendor +# and device codes in the subsystem ID. +# +# If you have older PMC EVR cards that do not have the MRF vendor and device +# IDs coded into their subsystem IDs, then select "PMC_SUBSYSTEM = PLX". +# The default is to instruct the configuration software to look for the MRF +# vendor and device IDs in the subsystem ID field. +# +# Note that you can not have both types of cards in your system or the +# configuration and initialization software will not be able to locate all +# of them. If you are running with older PMC EVR cards and acquire some newer +# cards that do have the MRF vendor and device IDs, you should use the +# "mrfUpdateMrfSubsystemId()" routine (callable from the IOC shell) to upgrade +# all your older cards with the MRF vendor and device IDs. + +#PMC_SUBSYSTEM_ID = PLX + +#------------------------------------------------------------------------------ +# Question 2: Does an offset need to be added to the PMC EVR's interrupt +# vector? +# +# The answer to this question is "probably not", unless you are running with +# an APS-customized BSP. These BSP's relocate the system interrupt vectors +# (including the vectors for the PCI interrupt lines) so that they are all +# at 0x100 and above. The problem is that the interrupt line register in PCI +# configuration space is only 8-bits wide, and will only contain the low-order +# byte of the interrupt vector number. +# +# If your BSP maps the PCI interrupt vectors above 0x100, uncomment the line +# below so that the correct high-order offset is added to the interrupt +# vector stored in PCI configuration space. This will ensure that +# mrfGetPmcErVector() will return the correct interrupt vector. +# +# The default is to return the 8-bit autoconfigured value. + +#PMC_INT_VECTOR_OFFSET = 0x100 + + +############################################################################### +# PART III -- Event Clock Speed +#============================================================================== +# The "Event Clock" value determines the maximum rate at which the event +# system can deliver events. The event clock is usually derived from the +# accelerator RF frequency by feeding an RF reference signal into the "RFIN" +# LEMO input on the front of the Event Generator board and dividing it down to +# a reasonable value. Currently, the RFIN signal can be divided by 4, 5, 6, +# 8, 10, or 12. We hope to be able to have "1" as the divisor in a future +# release. For the MRF 200 series, the maximum event clock rate is 125 MHz. +# +# The Event Receiver cards use a Micrel SY87739L Fractional-N Synthesizer chip +# to stay in synch with the Event Generator. The Fractional Synthesizer chip +# must be programmed to produce the same frequency (within +/- 100 parts-per- +# million) as the event clock generated in the Event Generator card. +# +# The Event Generator cards have the same fractional synthesizer chip, which +# can be used to generate the event clock if there is no RFIN signal. +# +# This section of the configuration file contains two ways to specify the event +# clock speed. It can be specified directly as a floating point number in +# megahertz, or it can be specified indirectly by providing the SY87739L +# control word that generates the desired frequency. Either method or both +# may be used. +# +# The preferred (and simpler) method is to just specify the EVENT_CLOCK_FREQ +# in megahertz and let the card initialization software compute the fractional +# synthesizer control word. +# +# In some cases it may be preferable to input the fractional synthesizer +# control word directly (e.g., the software has a bug and doesn't produce the +# correct control word, or there is to much jitter using the control word it +# does produce, or you just really like the control word you worked so hard to +# come up with). If this is the case, you may specify a FRAC_SYNTH_CONTROL +# value directly as a hexadecimal number. +# +# If you specify both an EVENT_CLOCK_FREQ value and a FRAC_SYNTH_CONTROL +# value, the card initialization software will check to make sure that the +# frequency generated by the FRAC_SYNTH_CONTROL word is within +/- 100 ppm +# of the frequency specified by the EVENT_CLOCK_FREQ parameter and display +# a warning message on the IOC console if it is not. +# +# If neither an event clock speed or a fractional synthesizer control word is +# specified in this section, the event clock speed (and control word) defaults +# to 125.0 MHz. +# + +#------------------------------------------------------------------------------ +# Question 1: What speed should the event clock run at (in MegaHertz)? +# +# The value selected below will be used to program the Micrel SY87739L +# chip on both the Event Receiver and Event Generator cards unless you +# also specify a fractional synthesizer control word. This value is also +# used by the software to translate between event clock units and real-time +# units (e.g., microseconds, milliseconds, fortnights, etc.) so it is +# important that this number represents the actual event clock speed as +# generated in the Event Generator card (e.g. based on the divided-down RFIN +# signal) rather than the frequency generated by the fractional synthesizer +# (which may be up to 100 ppm different). +# + +#EVENT_CLOCK_FREQ = 125.00 #MHz. +EVENT_CLOCK_FREQ = 114.24 #MHz. +#------------------------------------------------------------------------------ +# Question 2: Do you wish to specify your own value for the fractional +# synthesizer control word? +# +# Normally, you should not have to do this, but if you do need to, then enter +# your own control word value below. +# +# The fractional synthesizer control word must produce a frequency that is +# within +/- 100 parts-per-million of the event clock frequency generated by +# the Event Generator card, otherwise the the Event receiver cards will not be +# able to synchronize themselves to the event link. + +#FRAC_SYNTH_CONTROL = 0x00DE816D # 125.00 MHz. +FRAC_SYNTH_CONTROL = 0x0205C16D + +############################################################################### +# PART IV -- Time Stamping +#============================================================================== +# This section determines how timestamps are transmitted from the Event +# Generator and received by the Event Receiver boards. Timestamps have two +# components, which roughly correspond to the fields in an epicsTimeStamp +# structure. The low-order field of the timestamp is a counter that can +# count either: +# a) Timestamp events (event code 0x7C), +# b) A clock signal distributed on bit 4 of the distributed data bus, or +# c) Scaled event clock ticks. +# This field roughly corresponds to the "nanoseconds" field of the +# epicsTimeStamp structure. +# +# The high-order field of the timestamp corresponds to the "seconds" field +# of the epicsTimeStamp structure. Its value is loaded serially into a shift +# register by a series of 0x70 and 0x71 event codes. Event code 0x70 loads +# a 0 into the shift register and event code 0x71 loads a 1. Event code 0x7D +# latches the seconds field from the shift register and clears the low-order +# counter register. +# +# The Event Generator, generally just has to worry about generating the various +# timestamp events (0x70, 0x71, 0x7C, 0x7D) at the appropriate times. To aid +# in the use of external timestamp generators, the Event Generator has a mode +# which allows you to generate the "seconds counter" events (0x70 and 0x71) +# with TTL signals into the DBUS6 and DBUS7 inputs, and the "timestamp reset" +# event (0x7D) with a TTL signal into the DBUS5 input. This feature originated +# at the Diamond Light Source and is therefore referred to as the "Diamond +# Method". +# + +#------------------------------------------------------------------------------ +# Question 1: What should the Event Receiver cards count for the low-order +# 32-bits of the timestamp? +# +# Select one of the three options below (timestamp events, a clock signal +# on bit 4 of the distributed data bus, or scaled event clock ticks). +# +# The default is event clock ticks if no selection is made. +# +# Note that for Event Receiver firmware revisions D308 and lower, there is +# a problem with using the scaled event clock for timestamping. If you wish +# to use the scaled event clock, you will get best results by selecting a +# scale factor of 2 and the "RAW" conversion factor when answering questions +# 2 and 3 below (these are the defaults). +# + +#TS_FINE_COUNTER = EVR_TS_COUNTS_EVENT_CLOCK # Count (scaled) event clock ticks +#TS_FINE_COUNTER = EVR_TS_COUNTS_EVENTS # Count timestamp events (0x7C) +#TS_FINE_COUNTER = EVR_TS_COUNTS_DBUS4 # Count clock signal on DBUS bit 4 + + +#------------------------------------------------------------------------------ +# Question 2: If the Event Receiver low-order timestamp is counting +# event clock ticks, what scale factor should be applied? +# +# This question only needs to be answered if you selected +# "EVR_TS_COUNTS_EVENT_CLOCK" (either deliberately, or by default) +# in the answer to Question 1 above. +# +# At present, the fastest rate you can count is every other event clock +# (scale = 2). +# +# Uncomment the line below and assign the scaling value of your choice. +# The value you select should be an integer number between 1 and 65535. +# A value of 2 will count alternate event clocks. A value of 3 will count +# every third event clock, etc. +# +# The default value, if no selection is made, is to count every other event +# clock. +# + +#TS_EVENT_CLOCK_SCALE = 2 # Default, count alternate event clocks + + +#------------------------------------------------------------------------------ +# Question 3: What is the frequency (in MHz) of the clock source for the +# low-order 32 bits of the timestamp counter? +# +# This value is used to convert the clock ticks in the low-order 32 bits of +# the timestamp into the "nano-seconds" field of the epicsTimeStamp structure. +# If the resulting value is larger than 1.0e9, the excess value will cause +# the "seconds" field to increment. +# +# The value may be specified as "RAW, "AUTO", or a floating point number. +# If no value is specified, the default is to do no conversion and just return +# raw counts ("RAW" option). +# +# If you are using the (scaled) event clock for your counter (i.e. you +# selected TS_FINE_COUTER = EVR_TS_COUNTS_EVENT_CLOCK in question 1 above), +# you may specify "AUTO" and the software will compute the clock frequency +# for you by dividing the event clock frequency by the TS_EVENT_CLOCK_SCALE +# value. +# + +#TS_COUNT_FREQUENCY = RAW # Do not convert to ns (use raw counts) +#TS_COUNT_FREQUENCY = AUTO # Compute the freq (only if using event clock) +#TS_COUNT_FREQUENCY = 1 # Clock frequency is 1 MHz + + +#------------------------------------------------------------------------------ +# Question 4: Should the timestamp be latched on every read? +# +# When the routine, ErGetTimeStamp, is called to read the current timestamp +# (as opposed to an event timestamp) it can either latch the timestamp before +# reading it or just return a previously latched timestamp. Calling +# ErGetTimeStamp to read the current time is typically done to set the +# timestamp field during EPICS record processing, so how you answer this +# question will most likely depend on how you want your EPICS record timestamps +# handled. If you want the default EPICS timestamp behavior (each record's +# timestamp reflects the actual time it was processed, answer "YES" to this +# question. On the other hand, if you want (for example) all records +# processed during a single machine cycle to have the same timestamp (e.g. +# for correlation purposes), then you should answer "NO" to this question. +# +# Note that if you answer "NO" to this question, you will need to provide an +# alternate method for latching the timestamp such as manual latching +# by calling ErLatchTimeStamp, or setting up an event code to latch the +# timestamp. +# +# Also note that this question does not pertain to "event timestamps", which +# are stored in the FIFO and always reflect the time that the event occurred. +# +# Select one of the two options below (YES or NO) by uncommenting the +# appropriate line. If no selection is made, the default is to latch the +# timestamp on every read (YES). +# + +#TS_LATCH_ON_READ = YES +#TS_LATCH_ON_READ = NO + + +#------------------------------------------------------------------------------ +# Question 5: Should the Event Generator use the Distributed Data Bus +# inputs 4-7 to generate the timestamp (the Diamond Method)? +# +# If the "Diamond Method" is selected, the Event Generator will use the +# Distributed Data Bus inputs 4-7 to generate the timestamp. Some special +# hardware is required to use the "Diamond Method", but it allows you to have +# a completely automatic timestamp system, with no software intervention +# required. +# +# Under the "Diamond Method", a clock signal on Distribute Data Bus input 5 +# will generate a "Timestamp Reset" event (0x7D). Distributed Data Bus inputs +# 6 and 7 generate the '0' and '1' "Seconds Counter" events (0x70 and 0x71 +# respectively). Special hardware is required to generate these signals +# from an external time source such as a GPS. +# +# Distributed Data Bus input 4 can be used to generate the "high frequency" +# (low-order 32 bits) component of the timestamp. This is not strictly +# required, but is a convenient method of distributing the high-frequency +# clock. If you do use Distributed Data Bus input 4 for the high-frequency +# clock component, you should select +# TS_FINE_COUNTER = EVR_TS_COUNTS_DBUS4 +# when you answer question 1 above. +# +# Select one of the two options below (normal method or diamond method) +# The default value, if no selection is made, is to use the "Normal" method +# of generating the timestamp (explicitly generated timestamp events). + +#TS_GENERATION = EVG_TS_NORMAL_METHOD +#TS_GENERATION = EVG_TS_DIAMOND_METHOD + + +#------------------------------------------------------------------------------ +# Question 6: What is the Format of the "Seconds" Portion of the Timestamp? +# +# The "seconds" portion of the timestamp is the high-order 32 bits and is +# loaded into the Event Receiver using event codes 0x70 and 0x71. +# The answer to this question will determine how the routine, ErGetTimeStamp(), +# operates. +# +# ErGetTimeStamp() always returns "EPICS Time", in which the high-order +# 32 bits represents the number of seconds from the EPICS epoch (Midnight, +# January 1, 1990). If the "seconds" portion of the timestamp is in some +# other format (e.g. Unix time), the ErGetTimeStamp will need to translate +# it into EPICS time. +# +# The current choices for TS_SECONDS_FORMAT are: +# UNIX_TIME - Seconds past midnight, January 1, 1970 +# EPICS_TIME - Seconds past midnight, January 1, 1990 +# NONE - Seconds portion is not transmitted on the event link. +# +# The "NONE" option is useful for those systems which keep track of seconds +# in an alternative way such as ethernet broadcast, data buffer field, NTP, +# etc. +# +# Select one of the options below to indicate which format is used to transmit +# the seconds portion of the timestamp on the event link. The default is +# NONE if no selection is made. +# + +#TS_SECONDS_FORMAT = UNIX_TIME +#TS_SECONDS_FORMAT = EPICS_TIME +#TS_SECONDS_FORMAT = NONE + +#------------------------------------------------------------------------------ +# Question 7: Should the Event Receivers use the Heartbeat Event (0x7A) +# to determine whether the timestamp is valid? +# +# If software is involved on the Event Generator system to update the +# timestamps (eg. sending events to update the "seconds" or "ticks" field, +# using the data buffer to send the timestamp, etc.), then the heartbeat +# event can be used by the ErGetTimeStamp() routine to help determine +# whether or not the timestamp is valid. +# +# Setting TS_HEARTBEAT_CHECK = YES will allow the ErGetTimeStamp() routine +# to check for heartbeat timeouts as part of the determination on whether +# the current timestamp can be trusted. +# +# The default value is TS_HEARTBEAT_CHECK = NO. +# +# Note that setting TS_HEARTBEAT_CHECK = YES will automatically set +# ENABLE_HEARTBEAT = YES, overriding how it is set in Part V, Question 2 +# below. +# + +#TS_HEARTBEAT_CHECK = NO +#TS_HEARTBEAT_CHECK = YES + + + +############################################################################### +# PART V -- Miscellaneous Options +#============================================================================== + +#------------------------------------------------------------------------------ +# Question 1: Should the driver software use synchronous read and write +# operations when addressing the hardware. +# +# Synchronous reads and writes will guarantee the every I/O operation +# will be executed in the order that it was specified in the driver code +# (i.e., no I/O rearrangement due to pipelining). This is usually only +# important in interrupt service routines. However, if things are behaving +# poorly and you want to rule out I/O re-ordering, you can (with some +# performance degradation) do so by selecting: +# SYNC_IO = YES +# The default is to only use synchronous I/O when it is explicitly requested +# in the code (SYNC_IO = NO) +# + +#SYNC_IO = NO +#SYNC_IO = YES + +#------------------------------------------------------------------------------ +# Question 2: Should the Heartbeat Event (0x7A) be enabled on Event Receivers? +# +# The heartbeat event (0x7A) can be used to determine whether the software +# on the event generator system is running. This can be a useful feature +# to determine things like whether your timestamps are being updated, wether +# the data buffer is being updated, or even whether you are getting all the +# events you expect. If the Event Generator does not send a timestamp event +# after approximately 1.6 seconds, the Event Receiver will set a "No Heartbeat" +# flag in the control register and can also trigger a "No Heartbeat" interrupt. +# +# Selecting: +# ENABLE_HEARTBEAT = YES +# will enable the heartbeat interrupt on the Event Receiver. Site-specific +# code can be notified of heartbeat errors by calling ErRegisterErrorHandler() +# to register an error handling function. The error handling function can +# recognize heartbeat errors by checking to see if the error type has the +# value "ERROR_HEART". +# +# The default value is ENABLE_HEARTBEAT = NO (unless TS_HEARTBEAT_CHECK = YES +# in Part IV, Question 7 above). +# + +#ENABLE_HEARTBEAT = NO +#ENABLE_HEARTBEAT = YES diff -urN src.org/Makefile src/Makefile --- src.org/Makefile 2008-05-31 06:23:11.000000000 +0900 +++ src/Makefile 2008-09-10 10:23:33.000000000 +0900 @@ -62,18 +62,31 @@ CUSTOM_RECORDS += erRecord CUSTOM_RECORDS += ereventRecord +devMrfEg_SRCS += devMrfEg.c #--------------------- # Install DBD files # -DBD += mrfCommon.dbd +Xapp_DBD += base.dbd -DBD += drvMrfEg.dbd -DBD += devMrfEg.dbd -DBD += mrfEg.dbd - -DBD += drvMrfEr.dbd -DBD += devMrfEr.dbd -DBD += mrfEr.dbd +Xapp_DBD += mrfCommon.dbd +Xapp_DBD += egRecord.dbd +Xapp_DBD += erRecord.dbd +Xapp_DBD += egeventRecord.dbd +Xapp_DBD += ereventRecord.dbd + +Xapp_DBD += drvMrfEg.dbd +Xapp_DBD += devMrfEg.dbd +Xapp_DBD += devMrfEgEvent.dbd +Xapp_DBD += eventRecord.dbd +#Xapp_DBD += mrfEg.dbd + +Xapp_DBD += drvMrfEr.dbd +Xapp_DBD += devMrfEr.dbd + +Xapp_DBD += devPvme323Ao.dbd +Xapp_DBD += devPvme303.dbd +Xapp_DBD += devRpv130.dbd +#Xapp_DBD += mrfEr.dbd #--------------------- # Install DBD Header Files @@ -95,8 +108,14 @@ #--------------------- # Build the Event Generator Library # -PROD_IOC_vxWorks += mrfEgLib -LIBRARY_IOC += mrfEg +#PROD_IOC_vxWorks += mrfEgLib +#LIBRARY_IOC += mrfEg + +PROD_IOC = Xapp +# Xapp.dbd will be created and installed +DBD += Xapp.dbd +#Xapp_DBD += base.dbd + mrfEg_OBJS += drvMrfEg mrfEg_OBJS += devMrfEg @@ -105,17 +124,17 @@ mrfEg_OBJS += egRecord mrfEg_OBJS += egeventRecord -mrfEgLib_OBJS += $(mrfEg_OBJS) -mrfEgLib_OBJS += $(mrfCommon_OBJS) -mrfEgLib_SRCS += mrfEg_registerRecordDeviceDriver.cpp +#mrfEgLib_OBJS += $(mrfEg_OBJS) +#mrfEgLib_OBJS += $(mrfCommon_OBJS) +#mrfEgLib_SRCS += mrfEg_registerRecordDeviceDriver.cpp OBJS_IOC += $(mrfEg_OBJS) #--------------------- # Build the Event Receiver Library # -PROD_IOC_vxWorks += mrfErLib -LIBRARY_IOC += mrfEr +#PROD_IOC_vxWorks += mrfErLib +#LIBRARY_IOC += mrfEr mrfEr_OBJS += drvMrfEr mrfEr_OBJS += mrfPmc @@ -124,11 +143,16 @@ mrfEr_OBJS += erRecord mrfEr_OBJS += ereventRecord -mrfErLib_OBJS += $(mrfEr_OBJS) -mrfErLib_OBJS += $(mrfCommon_OBJS) -mrfErLib_SRCS += mrfEr_registerRecordDeviceDriver.cpp +#mrfErLib_OBJS += $(mrfEr_OBJS) +#mrfErLib_OBJS += $(mrfCommon_OBJS) +#mrfErLib_SRCS += mrfEr_registerRecordDeviceDriver.cpp OBJS_IOC += $(mrfEr_OBJS) +Xapp_OBJS += $(mrfEg_OBJS) +Xapp_OBJS += $(mrfEr_OBJS) +Xapp_OBJS += $(mrfCommon_OBJS) +Xapp_SRCS += Xapp_registerRecordDeviceDriver.cpp + #--------------------- # Build the host-side utilities for creating and analyzing @@ -155,6 +179,7 @@ INC += devMrfEr.h INC += debugPrint.h +Xapp_LIBS += $(EPICS_BASE_IOC_LIBS) pvme323 pvme303 rpv130 #=======================================================================# # RULES # diff -urN src.org/devMrfEg.c src/devMrfEg.c --- src.org/devMrfEg.c 2008-05-31 06:23:08.000000000 +0900 +++ src/devMrfEg.c 2008-09-10 10:23:33.000000000 +0900 @@ -511,6 +511,9 @@ */ pRec->lclk = EgGetEventClockSource (pCard); pRec->ldiv = EgGetRfDivider (pCard); + pRec->ltcs = EgGetTransRef (pCard); + pRec->lecs = EgGetEventClock (pCard); + pRec->lbrs = EgGetBrefClock (pCard); /*--------------------- * Initialize the last external trigger enable fields from the hardware @@ -752,6 +755,40 @@ DEBUGPRINT (DP_DEBUG, DebugFlag, (" EgProcess(%s): RF Divider = %d\n", pRec->name, pRec->rdiv)); }/*end if event clock source and/or RF input divider changed*/ + /*--------------------- + * Transmitter reference clock select + */ + if (pRec->tcsl != pRec->ltcs) { + pRec->ltcs = pRec->tcsl; + EgSetTransRef (pCard, pRec->tcsl); + db_post_events (pRec, &pRec->tcsl, DBE_VALUE|DBE_LOG); + DEBUGPRINT (DP_DEBUG, DebugFlag, + (" EgProcess(%s): Transmitter reference select %s \n", + pRec->name, (menuNO == pRec->tcsl) ? "is not" : "is")); + }/*end if Transmitter reference clock select*/ + /*--------------------- + * Event clock select + */ + if (pRec->ecsl != pRec->lecs) { + pRec->lecs = pRec->ecsl; + EgSetEventClock (pCard, pRec->ecsl); + db_post_events (pRec, &pRec->ecsl, DBE_VALUE|DBE_LOG); + DEBUGPRINT (DP_DEBUG, DebugFlag, + (" EgProcess(%s): Event clock select %s \n", + pRec->name, (menuNO == pRec->ecsl) ? "is not" : "is")); + }/*end if Event clock select*/ + /*--------------------- + * BREFCLK2 source select + */ + if (pRec->brsl != pRec->lbrs) { + pRec->lbrs = pRec->brsl; + EgSetBrefClock (pCard, pRec->brsl); + db_post_events (pRec, &pRec->brsl, DBE_VALUE|DBE_LOG); + DEBUGPRINT (DP_DEBUG, DebugFlag, + (" EgProcess(%s): BREFCLK2 source select %s \n", + pRec->name, (menuNO == pRec->brsl) ? "is not" : "is")); + }/*end if BREFCLK2 source select*/ + /*--------------------- * Check to see if the upstream event link FIFO enable field changed diff -urN src.org/devMrfEr.c src/devMrfEr.c --- src.org/devMrfEr.c 2008-05-31 06:23:09.000000000 +0900 +++ src/devMrfEr.c 2008-09-10 10:23:34.000000000 +0900 @@ -96,7 +96,6 @@ #include /* EPICS Symbol exporting macro definitions */ - /**************************************************************************************************/ /* Prototype Function Declarations */ /**************************************************************************************************/ @@ -330,7 +329,9 @@ */ if (!pRec->enab & ErMasterEnableGet(pCard)) ErMasterEnableSet (pCard, epicsFalse); - + + + /*--------------------- * Set the trigger event output enables */ @@ -406,6 +407,13 @@ ErSetFPMap (pCard, 4, pRec->fps4); ErSetFPMap (pCard, 5, pRec->fps5); ErSetFPMap (pCard, 6, pRec->fps6); + ErSetFPMap (pCard, 7, pRec->fps7); + ErSetFPMap (pCard, 8, pRec->fps8); + ErSetFPMap (pCard, 9, pRec->fps9); + ErSetFPMap (pCard, 10, pRec->fpsa); + ErSetFPMap (pCard, 11, pRec->fpsb); + ErSetFPMap (pCard, 12, pRec->fpsc); + ErSetFPMap (pCard, 13, pRec->fpsd); /*--------------------- * Enable or Disable Receive Link Frame Error Interrupts diff -urN src.org/drvMrfEg.c src/drvMrfEg.c --- src.org/drvMrfEg.c 2008-05-31 06:23:10.000000000 +0900 +++ src/drvMrfEg.c 2008-09-10 10:23:34.000000000 +0900 @@ -555,71 +555,69 @@ /**************************************************************************************************/ /* RF Clock Select Register (0x040) Bit Assignments */ /**************************************************************************************************/ +#define EVG_RFSEL_TCSEL_MASK 0x0100 /* Transmitter referebce select. */ +#define EVG_RFSEL_ECSEL_MASK 0x0080 /* Event clock select */ +#define EVG_RFSEL_BRSEL_MASK 0x0040 /* Transmitted data select mask */ +#define EVG_RFSEL_RFSEL_MASK 0x003F /* RF input divider select mask */ +#define EVG_RFSEL_RFDIV_MASK 0x003F /* RF input divider select mask */ -#define EVG_RFSEL_TRSEL_MASK 0x0080 /* Transceiver select. */ -#define EVG_RFSEL_GSEL_MASK 0x0040 /* Gigabit clock source select */ -#define EVG_RFSEL_TXSEL_MASK 0x0030 /* Transmitted data select mask */ -#define EVG_RFSEL_RFSEL_MASK 0x000C /* Event clock RF source select mask */ -#define EVG_RFSEL_DIV_MASK 0x0003 /* RF input divider select mask */ /*--------------------- - * Define Transceiver Select Values + * Define Transmitter Reference Select Values */ -#define EVG_RFSEL_TRSEL_SMFF 0x0000 /* Small Form Factor Plugabble Transceiver (up to 2.5 GHz)*/ -#define EVG_RFSEL_TRSEL_SCX 0x0080 /* 1x9 Duplex SC Transceiver (up to 1.25 GHz) */ +#define EVG_RFSEL_TCSEL_FRAC 0x0000 /* Transmitter reference clock normal operation */ +#define EVG_RFSEL_TCSEL_EXT 0x0100 /* Transmitter reference clock external RF */ /*--------------------- - * Define Transmitted Data Selection Values + * Define Event Clock Select Values */ -#define EVG_RFSEL_TXSEL_ADN 0x0000 /* Data transmitted through ADN2812 */ -#define EVG_RFSEL_TXSEL_MGT 0x0010 /* Data transmitted directly from MGT */ -#define EVG_RFSEL_TXSEL_BC 0x0020 /* Data transmitted synchronized to bit clock */ -#define EVG_RFSEL_TXSEL_LOOP 0x0030 /* Loop back received data */ +#define EVG_RFSEL_ECSEL_FRAC 0x0000 /* Event clock on-chip fractional synthesizer */ +#define EVG_RFSEL_ECSEL_EXT 0x0080 /* Event clock on-chip external RF */ /*--------------------- - * Define Event Clock Source Selection Values + * Define BREFCLK2 Source Select Values */ -#define EVG_RFSEL_CLOCK_DIV2 0x0000 /* Use RF Input divided by 8, 10, or 12 */ -#define EVG_RFSEL_CLOCK_FRAC 0x0004 /* Use fractional synthesizer output */ -#define EVG_RFSEL_CLOCK_LVP 0x0008 /* Use LVPECL oscillator */ -#define EVG_RFSEL_CLOCK_DIV1 0x000C /* Use RF Input divided by 4, 5, or 6 */ -#define EVG_RFSEL_CLOCK_EVG 0x0040 /* Lock Gigabit clock to upstream EVG */ +#define EVG_RFSEL_BRSEL_REC 0x0000 /* BREFCLK2 source select */ +#define EVG_RFSEL_BRSEL_EXT 0x0040 /* BREFCLK2 source select */ +#define EVG_RFSEL_CLOCK_DIV1 0x01C0 +#define EVG_RFSEL_CLOCK_FRAC 0x0000 +#define EVG_RFSEL_CLOCK_EVG 0x0180 /*--------------------- * Define RF Input Divider Selection Values */ -#define EVG_RFSEL_DIV_4_8 0x0000 /* Divide RF input by 4 or 8 */ -#define EVG_RFSEL_DIV_6_12 0x0001 /* Divide RF input by 6 or 12 */ -#define EVG_RFSEL_DIV_5_10 0x0002 /* Divide RF input by 5 or 10 */ -#define EVG_RFSEL_DIV_10_5 0x0003 /* Divide RF input by 5 or 10 */ +#define EVG_RFSEL_DIV_1 0x0000 /* Divide RF input by 1 */ +#define EVG_RFSEL_DIV_2 0x0001 /* Divide RF input by 2 */ +#define EVG_RFSEL_DIV_3 0x0002 /* Divide RF input by 3 */ +#define EVG_RFSEL_DIV_4 0x0003 /* Divide RF input by 4 */ +#define EVG_RFSEL_DIV_5 0x0004 /* Divide RF input by 5 */ +#define EVG_RFSEL_DIV_6 0x0005 /* Divide RF input by 6 */ +#define EVG_RFSEL_DIV_7 0x0006 /* Divide RF input by 7 */ +#define EVG_RFSEL_DIV_8 0x0007 /* Divide RF input by 8 */ +#define EVG_RFSEL_DIV_9 0x0008 /* Divide RF input by 9 */ +#define EVG_RFSEL_DIV_10 0x0009 /* Divide RF input by 10 */ +#define EVG_RFSEL_DIV_11 0x000A /* Divide RF input by 11 */ +#define EVG_RFSEL_DIV_12 0x000B /* Divide RF input by 12 */ +#define EVG_RFSEL_DIV_13 0x000C /* OFF */ +#define EVG_RFSEL_DIV_14 0x000D /* Divide RF input by 14 */ +#define EVG_RFSEL_DIV_15 0x000E /* Divide RF input by 15 */ +#define EVG_RFSEL_DIV_16 0x000F /* Divide RF input by 16 */ +#define EVG_RFSEL_DIV_17 0x0010 /* Divide RF input by 17 */ +#define EVG_RFSEL_DIV_18 0x0011 /* Divide RF input by 18 */ +#define EVG_RFSEL_DIV_19 0x0012 /* Divide RF input by 19 */ +#define EVG_RFSEL_DIV_20 0x0013 /* Divide RF input by 20 */ /*--------------------- * Define Mask of Event Clock Source Selection Bits */ #define EVG_RFSEL_CLOCK_MASK ( /* Mask of event clock source selection bits */\ - EVG_RFSEL_GSEL_MASK | /* Upstream event link selection mask */\ - EVG_RFSEL_RFSEL_MASK ) /* RF and internal source selection mask */ - -/*--------------------- - * Define Mask of RF Input Divider Values - */ -#define EVG_RFSEL_RFDIV_MASK ( /* Mask of RF divider selection bits */\ - EVG_RFSEL_CLOCK_MASK | /* Event clock source selection mask */\ - EVG_RFSEL_DIV_MASK ) /* RF input divider selection mask */ - -/*--------------------- - * Define Values for RF Divisors - */ -#define EVG_RFSEL_DIV4 (EVG_RFSEL_DIV_4_8 | EVG_RFSEL_CLOCK_DIV1) /* Divide by 4 */ -#define EVG_RFSEL_DIV5 (EVG_RFSEL_DIV_5_10 | EVG_RFSEL_CLOCK_DIV1) /* Divide by 5 */ -#define EVG_RFSEL_DIV5A (EVG_RFSEL_DIV_10_5 | EVG_RFSEL_CLOCK_DIV1) /* Divide by 5 */ -#define EVG_RFSEL_DIV6 (EVG_RFSEL_DIV_6_12 | EVG_RFSEL_CLOCK_DIV1) /* Divide by 6 */ -#define EVG_RFSEL_DIV8 (EVG_RFSEL_DIV_4_8 | EVG_RFSEL_CLOCK_DIV2) /* Divide by 8 */ -#define EVG_RFSEL_DIV10 (EVG_RFSEL_DIV_5_10 | EVG_RFSEL_CLOCK_DIV2) /* Divide by 10 */ -#define EVG_RFSEL_DIV10A (EVG_RFSEL_DIV_10_5 | EVG_RFSEL_CLOCK_DIV2) /* Divide by 10 */ -#define EVG_RFSEL_DIV12 (EVG_RFSEL_DIV_6_12 | EVG_RFSEL_CLOCK_DIV2) /* Divide by 12 */ - - + EVG_RFSEL_TCSEL_MASK | /* */\ + EVG_RFSEL_ECSEL_MASK | /* */\ + EVG_RFSEL_BRSEL_MASK ) +#define EVG_RFSEL_FRAC_MASK ( \ + EVG_RFSEL_TCSEL_MASK | \ + EVG_RFSEL_ECSEL_MASK ) +#define EVG_RFSEL_UPS_MASK 0x1BF /**************************************************************************************************/ /* Data Buffer Control Register (0x06A) Bit Assignments */ /**************************************************************************************************/ @@ -2078,7 +2076,8 @@ */ epicsUInt16 ClockSource; /* Local copy of event clock selection bits */ register void *pEg = pCard->pEg; /* Pointer to Event Generator register map */ - + + /*--------------------- * Read the RF Selection register and extract the event clock selection bits */ @@ -2087,8 +2086,8 @@ /*--------------------- * Event clock is derived from the RF input */ - if ((EVG_RFSEL_CLOCK_DIV1 == ClockSource) || (EVG_RFSEL_CLOCK_DIV2 == ClockSource)) - return menuEventClockSrc_RF; + if (EVG_RFSEL_CLOCK_DIV1 == ClockSource) + return menuEventClockSrc_RF; /*--------------------- * Event clock is generated internally using the fractional synthesizer chip @@ -2096,12 +2095,7 @@ if (EVG_RFSEL_CLOCK_FRAC == ClockSource) return menuEventClockSrc_FracSynth; - /*--------------------- - * Event clock is generated by the LVPECL oscillator - */ - if (EVG_RFSEL_CLOCK_LVP == ClockSource) - return menuEventClockSrc_LVPECL; - + /*--------------------- * Event clock is derived from the upstream event link */ @@ -2158,26 +2152,66 @@ */ switch (RfSelect) { - case EVG_RFSEL_DIV4: /* RF Input is divided by 4 */ + case EVG_RFSEL_DIV_1: /* RF Input is divided by 1 */ + return 1; + + case EVG_RFSEL_DIV_2: /* RF Input is divided by 2 */ + return 2; + + case EVG_RFSEL_DIV_3: /* RF Input is divided by 3 */ + return 3; + + case EVG_RFSEL_DIV_4: /* RF Input is divided by 4 */ return 4; - case EVG_RFSEL_DIV5: /* RF Input is divided by 5 */ - case EVG_RFSEL_DIV5A: + case EVG_RFSEL_DIV_5: /* RF Input is divided by 5 */ return 5; - case EVG_RFSEL_DIV6: /* RF Input is divided by 6 */ - return 6; + case EVG_RFSEL_DIV_6: /* RF Input is divided by 6 */ + return 6; - case EVG_RFSEL_DIV8: /* RF Input is divided by 8 */ - return 8; + case EVG_RFSEL_DIV_7: /* RF Input is divided by 7 */ + return 7; - case EVG_RFSEL_DIV10: /* RF Input is divided by 10 */ - case EVG_RFSEL_DIV10A: + case EVG_RFSEL_DIV_8: /* RF Input is divided by 8 */ + return 8; + + case EVG_RFSEL_DIV_9: /* RF Input is divided by 9 */ + return 9; + + case EVG_RFSEL_DIV_10: /* RF Input is divided by 10 */ return 10; + + case EVG_RFSEL_DIV_11: /* RF Input is divided by 11 */ + return 11; - case EVG_RFSEL_DIV12: /* RF Input is divided by 12 */ + case EVG_RFSEL_DIV_12: /* RF Input is divided by 12 */ return 12; + case EVG_RFSEL_DIV_13: /* RF Input is divided by OFF */ + return 0; + + case EVG_RFSEL_DIV_14: /* RF Input is divided by 14 */ + return 14; + + case EVG_RFSEL_DIV_15: /* RF Input is divided by 15 */ + return 15; + + case EVG_RFSEL_DIV_16: /* RF Input is divided by 16 */ + return 16; + + case EVG_RFSEL_DIV_17: /* RF Input is divided by 17 */ + return 17; + + case EVG_RFSEL_DIV_18: /* RF Input is divided by 18 */ + return 18; + + case EVG_RFSEL_DIV_19: /* RF Input is divided by 19 */ + return 19; + + case EVG_RFSEL_DIV_20: /* RF Input is divided by 20 */ + return 20; + default: /* RF Input is not enabled */ return 0; @@ -2244,21 +2278,36 @@ /*--------------------- * Read the RF Selection register and mask out the event clock and RF divisor selection bits */ - RfSelect = MRF_READ16(pEg, RfSelect) & ~EVG_RFSEL_RFDIV_MASK; - + /*RfSelect = MRF_READ16(pEg, RfSelect) & ~EVG_RFSEL_RFDIV_MASK;*/ + + RfSelect = MRF_READ16(pEg, RfSelect); /*--------------------- * If "RF Input" is selected for the clock source, set the RfSelect register bits * based on the specified divisor. */ if (menuEventClockSrc_RF == ClockSource) { + RfSelect &= ~EVG_RFSEL_RFDIV_MASK; switch (RfDivide) { - case 4: RfSelect |= EVG_RFSEL_DIV4; break; - case 5: RfSelect |= EVG_RFSEL_DIV5; break; - case 6: RfSelect |= EVG_RFSEL_DIV6; break; - case 8: RfSelect |= EVG_RFSEL_DIV8; break; - case 10: RfSelect |= EVG_RFSEL_DIV10; break; - case 12: RfSelect |= EVG_RFSEL_DIV12; break; - + case 1: RfSelect |= (EVG_RFSEL_DIV_1|EVG_RFSEL_CLOCK_DIV1); break; + case 2: RfSelect |= (EVG_RFSEL_DIV_2|EVG_RFSEL_CLOCK_DIV1); break; + case 3: RfSelect |= (EVG_RFSEL_DIV_3|EVG_RFSEL_CLOCK_DIV1); break; + case 4: RfSelect |= (EVG_RFSEL_DIV_4|EVG_RFSEL_CLOCK_DIV1); break; + case 5: RfSelect |= (EVG_RFSEL_DIV_5|EVG_RFSEL_CLOCK_DIV1); break; + case 6: RfSelect |= (EVG_RFSEL_DIV_6|EVG_RFSEL_CLOCK_DIV1); break; + case 7: RfSelect |= (EVG_RFSEL_DIV_7|EVG_RFSEL_CLOCK_DIV1); break; + case 8: RfSelect |= (EVG_RFSEL_DIV_8|EVG_RFSEL_CLOCK_DIV1); break; + case 9: RfSelect |= (EVG_RFSEL_DIV_9|EVG_RFSEL_CLOCK_DIV1); break; + case 10: RfSelect |= (EVG_RFSEL_DIV_10|EVG_RFSEL_CLOCK_DIV1); break; + case 11: RfSelect |= (EVG_RFSEL_DIV_11|EVG_RFSEL_CLOCK_DIV1); break; + case 12: RfSelect |= (EVG_RFSEL_DIV_12|EVG_RFSEL_CLOCK_DIV1); break; + case 13: RfSelect |= (EVG_RFSEL_DIV_13|EVG_RFSEL_CLOCK_DIV1); break; + case 14: RfSelect |= (EVG_RFSEL_DIV_14|EVG_RFSEL_CLOCK_DIV1); break; + case 15: RfSelect |= (EVG_RFSEL_DIV_15|EVG_RFSEL_CLOCK_DIV1); break; + case 16: RfSelect |= (EVG_RFSEL_DIV_16|EVG_RFSEL_CLOCK_DIV1); break; + case 17: RfSelect |= (EVG_RFSEL_DIV_17|EVG_RFSEL_CLOCK_DIV1); break; + case 18: RfSelect |= (EVG_RFSEL_DIV_18|EVG_RFSEL_CLOCK_DIV1); break; + case 19: RfSelect |= (EVG_RFSEL_DIV_19|EVG_RFSEL_CLOCK_DIV1); break; + case 20: RfSelect |= (EVG_RFSEL_DIV_20|EVG_RFSEL_CLOCK_DIV1); break; /*--------------------- * Error: Unsupported divisor requested. * Return without doing anything. @@ -2278,19 +2327,14 @@ * Use the fractional synthesizer chip to generate the event clock. */ else if (menuEventClockSrc_FracSynth == ClockSource) - RfSelect |= EVG_RFSEL_CLOCK_FRAC; + RfSelect &= ~EVG_RFSEL_FRAC_MASK; /*--------------------- * Event clock is extracted from the upstream event link. */ else if (menuEventClockSrc_EventLink == ClockSource) - RfSelect |= EVG_RFSEL_CLOCK_EVG; + RfSelect &= EVG_RFSEL_UPS_MASK; - /*--------------------- - * Event clock is generated by the LVPECL oscillator - */ - else if (menuEventClockSrc_EventLink == ClockSource) - RfSelect |= EVG_RFSEL_CLOCK_LVP; /*--------------------- * Error: Invalid event clock source was specified. @@ -2309,6 +2353,91 @@ return ClockSource; }/*end EgSetEventClockSource()*/ + +menuYesNo EgGetTransRef (EgCardStruct *pCard) +{ + register void *pEg = pCard->pEg; + + if (MRF_READ16(pEg, RfSelect) & EVG_RFSEL_TCSEL_MASK) + return menuYES; + else + return menuNO; + +}/*EgGetTransRef()*/ + +void EgSetTransRef (EgCardStruct *pCard, menuYesNo Value) +{ + register void *pEg = pCard->pEg; + + if (menuYES == Value) + MRF_BITSET16 (pEg, RfSelect, EVG_RFSEL_TCSEL_EXT); + + else if (menuNO == Value) + MRF_BITCLR16 (pEg, RfSelect, EVG_RFSEL_TCSEL_FRAC); + + else + DEBUGPRINT (DP_ERROR, EgDebugFlag, + ("EgSetTransRef: ERROR - Invalid value for bypass enable/disable (%d)\n", + Value)); + +}/*end EgSetTransRef()*/ +menuYesNo EgGetEventClock (EgCardStruct *pCard) +{ + register void *pEg = pCard->pEg; + + if (MRF_READ16(pEg, RfSelect) & EVG_RFSEL_ECSEL_MASK) + return menuYES; + else + return menuNO; + +}/*EgGetEventClock()*/ + +void EgSetEventClock (EgCardStruct *pCard, menuYesNo Value) +{ + register void *pEg = pCard->pEg; + + if (menuYES == Value) + MRF_BITSET16 (pEg, RfSelect, EVG_RFSEL_ECSEL_FRAC); + + else if (menuNO == Value) + MRF_BITCLR16 (pEg, RfSelect, EVG_RFSEL_ECSEL_EXT); + + else + DEBUGPRINT (DP_ERROR, EgDebugFlag, + ("EgSetEventClock: ERROR - Invalid value for bypass enable/disable (%d)\n", + Value)); + +}/*end EgSetEventClock()*/ + +menuYesNo EgGetBrefClock (EgCardStruct *pCard) +{ + register void *pEg = pCard->pEg; + + if (MRF_READ16(pEg, RfSelect) & EVG_RFSEL_BRSEL_MASK) + return menuYES; + else + return menuNO; + +}/*EgGetTransRef()*/ + +void EgSetBrefClock (EgCardStruct *pCard, menuYesNo Value) +{ + register void *pEg = pCard->pEg; + + if (menuYES == Value) + MRF_BITSET16 (pEg, RfSelect, EVG_RFSEL_BRSEL_EXT); + + else if (menuNO == Value) + MRF_BITCLR16 (pEg, RfSelect, EVG_RFSEL_BRSEL_REC); + + else + DEBUGPRINT (DP_ERROR, EgDebugFlag, + ("EgSetBrefClock: ERROR - Invalid value for bypass enable/disable (%d)\n", + Value)); + +}/*end EgSetTransRef()*/ + + /** * @@ -4675,7 +4804,7 @@ * Set the RF clock selection regsiter to use the internal fractional synthesizer * and to transmit directly from the Multi-Gigabit Transceiver. */ - MRF_WRITE16 (pEg, RfSelect, (EVG_RFSEL_TXSEL_MGT | EVG_RFSEL_CLOCK_FRAC)); + /*MRF_WRITE16 (pEg, RfSelect, (EVG_RFSEL_TXSEL_MGT | EVG_RFSEL_CLOCK_FRAC));*/ /*--------------------- * Initialize AC Input control: @@ -5331,36 +5460,31 @@ */ printf ("Card status info: RF Select = %4.4X\n", rfSelect); - if (rfSelect & EVG_RFSEL_TRSEL_SCX) - printf (" 7: *1.25 Gbit transceiver selected\n"); - else printf (" 7: *2.5 Gbit transceiver selected\n"); - - if (rfSelect & EVG_RFSEL_GSEL_MASK) - printf (" 6: *Gigabit clock locked to upstream event link\n"); - else printf (" 6: *Gigabit clock locked to RF reference\n"); - - switch (rfSelect & EVG_RFSEL_TXSEL_MASK) { - case EVG_RFSEL_TXSEL_ADN: printf (" 4-5: *Data xmit through ADN2812\n"); break; - case EVG_RFSEL_TXSEL_MGT: printf (" 4-5: *Data xmit from gigabit transceiver\n"); break; - case EVG_RFSEL_TXSEL_BC: printf (" 4-5: *Data xmit synced with bit clock\n"); break; - case EVG_RFSEL_TXSEL_LOOP: printf (" 4-5: *Loop back received data \n"); break; - }/*end switch on transmit select bits*/ + if (rfSelect & EVG_RFSEL_TCSEL_MASK) + printf (" 8: *external RF/recoverd event clock from upstream EVG selected\n"); + else printf (" 8: *on-chip fractional synthesizer selected\n"); + + if (rfSelect & EVG_RFSEL_ECSEL_MASK) + printf (" 7: *external RF/recoverd event clock from upstream EVG selected\n"); + else printf (" 7: *on-chip fractional synthesizer selected\n"); + + if (rfSelect & EVG_RFSEL_BRSEL_MASK) + printf (" 6: *external RF\n"); + else printf (" 6: *recoverd event clock from upstream EVG selected\n"); + switch (clockSource) { case menuEventClockSrc_EventLink: - printf (" 0-3: *Event clock from upstream event link\n"); + printf (" 0-5: *Event clock from upstream event link\n"); break; case menuEventClockSrc_FracSynth: - printf (" 0-3: *Event clock from fractional synthesizer\n"); - break; - case menuEventClockSrc_LVPECL: - printf (" 0-3: *Event clock from LVPECL oscillator\n"); + printf (" 0-5: *Event clock from fractional synthesizer\n"); break; case menuEventClockSrc_RF: - printf (" 0-3: *Event clock from RF input divided by %d\n", EgGetRfDivider(pCard)); + printf (" 0-5: *Event clock from RF input divided by %d\n", EgGetRfDivider(pCard)); break; default: - printf (" 0-3: *Event clock source not known\n"); + printf (" 0-5: *Event clock source not known\n"); break; }/*end switch on event clock source*/ diff -urN src.org/drvMrfEg.h src/drvMrfEg.h --- src.org/drvMrfEg.h 2008-05-31 06:23:10.000000000 +0900 +++ src/drvMrfEg.h 2008-09-10 10:23:34.000000000 +0900 @@ -284,5 +284,10 @@ menuYesNo EgGetRxError (EgCardStruct*); void EgResetAll (EgCardStruct*); void EgSetTSSeconds (EgCardStruct*, epicsUInt32); - +menuYesNo EgGetTransRef (EgCardStruct*); +void EgSetTransRef (EgCardStruct*, menuYesNo); +menuYesNo EgGetEventClock (EgCardStruct*); +void EgSetEventClock (EgCardStruct*, menuYesNo); +menuYesNo EgGetBrefClock (EgCardStruct*); +void EgSetBrefClock (EgCardStruct*, menuYesNo); #endif diff -urN src.org/egRecord.dbd src/egRecord.dbd --- src.org/egRecord.dbd 2008-05-31 06:23:08.000000000 +0900 +++ src/egRecord.dbd 2008-09-10 10:23:34.000000000 +0900 @@ -799,6 +799,45 @@ prompt("Last RF Input Divider") interest(4) } + field(TCSL,DBF_MENU) { + prompt("Transmmiter Reference Clock Select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + menu(menuYesNo) + initial("NO") + } + field(LTCS,DBF_MENU) { + prompt("Last Transmmiter Reference Clock Select") + interest(4) + menu(menuYesNo) + } + field(ECSL,DBF_MENU) { + prompt("Event Clock Select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + menu(menuYesNo) + initial("NO") + } + field(LECS,DBF_MENU) { + prompt("Last Event Clock Select") + interest(4) + menu(menuYesNo) + } + field(BRSL,DBF_MENU) { + prompt("BREFCLK2 Source Select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + menu(menuYesNo) + initial("NO") + } + field(LBRS,DBF_MENU) { + prompt("Last BREFCLK2 Source Select") + interest(4) + menu(menuYesNo) + } # # "Reset" Fields # diff -urN src.org/erRecord.dbd src/erRecord.dbd --- src.org/erRecord.dbd 2008-05-31 06:23:09.000000000 +0900 +++ src/erRecord.dbd 2008-09-10 10:23:34.000000000 +0900 @@ -360,7 +360,7 @@ promptgroup(GUI_DISPLAY) pp(TRUE) interest(1) - } + } field(OT1D,DBF_ULONG) { prompt("OTP 1 Delay") promptgroup(GUI_DISPLAY) @@ -824,6 +824,49 @@ interest(1) } + field(FPS7,DBF_USHORT) { + prompt("Front Panel output 7 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + field(FPS8,DBF_USHORT) { + prompt("Front Panel output 8 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + field(FPS9,DBF_USHORT) { + prompt("Front Panel output 9 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + field(FPSA,DBF_USHORT) { + prompt("Front Panel output 10 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + field(FPSB,DBF_USHORT) { + prompt("Front Panel output 11 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + field(FPSC,DBF_USHORT) { + prompt("Front Panel output 12 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + field(FPSD,DBF_USHORT) { + prompt("Front Panel output 13 select") + promptgroup(GUI_DISPLAY) + pp(TRUE) + interest(1) + } + } diff -urN src.org/menuEventClockSrc.dbd src/menuEventClockSrc.dbd --- src.org/menuEventClockSrc.dbd 2008-05-31 06:23:08.000000000 +0900 +++ src/menuEventClockSrc.dbd 2008-09-10 10:23:34.000000000 +0900 @@ -1,7 +1,6 @@ menu (menuEventClockSrc) { choice(menuEventClockSrc_FracSynth,"Fractional Synthesizer") choice(menuEventClockSrc_RF,"RF Input") - choice(menuEventClockSrc_LVPECL,"LVPECL Oscillator") choice(menuEventClockSrc_EventLink,"Upstream Event Link") choice(menuEventClockSrc_None,"None") } diff -urN src.org/mrfPmc.c src/mrfPmc.c --- src.org/mrfPmc.c 2008-05-31 06:23:11.000000000 +0900 +++ src/mrfPmc.c 2008-09-10 10:23:34.000000000 +0900 @@ -603,10 +603,11 @@ */ status = getAnswer (Answer, sizeof(Answer)); if ((OK != status) || (strcmp(Answer, "Y") && strcmp(Answer, "y"))) { - printf (" -- Answer was not 'Y' or 'y'. Subsystem ID will not be changed.\n"); + printf (" -- Answer was not 'Y' or 'y'. Serial number will not be written.\n"); continue; }/*end if answer was not 'Y' or 'y'*/ + else continue; /******************************************************************************************/ /* All sanity checks have passed and the caller has given permission. */